Metal-oxide-semiconductor (MOS) devices are basic building elements in integrated circuits. A conventional MOS device typically has a gate electrode formed of polysilicon and doped with p-type or n-type impurities using doping operations such as ion implantation or thermal diffusion. It is preferred to adjust the work function of the gate electrode to the band-edge of the silicon. For an NMOS device, the work function of the gate electrode is preferably adjusted to close to the conduction band, and for a PMOS device, the work function of the gate electrode is preferably adjusted to close to the valence band. Adjusting the work function of the polysilicon gate electrode can be achieved by selecting appropriate impurities.
MOS devices with polysilicon gate electrodes exhibit a carrier depletion effect, which is also referred to as a poly depletion effect. The poly depletion effect occurs when applied electrical fields sweep away carriers from regions close to gate dielectrics, forming depletion layers. In an n-doped polysilicon layer, the depletion layer includes ionized non-mobile donor sites, whereas in a p-doped polysilicon layer, the depletion layer includes ionized non-mobile acceptor sites. The depletion effect results in an increase in the effective gate dielectric thickness, making it more difficult for an inversion layer to be created at the surface of the semiconductor substrate.
The poly depletion effect was previously solved by forming metal gate electrodes based on the art of replacement gate (RPG) or gate-first approaches. Fully silicided (FUSI) gate electrodes may also be used to eliminate the poly depletion effect. The metallic gates used in NMOS devices and PMOS devices by the above-mentioned approaches also preferably have band-edge work functions. Among these approaches, RPG and FUSI have shown a complexity in CMOS process flow and a high cost for manufacture. Contrary to RPG and FUSI, the gate-first approaches have the advantages of low cost and simple integrated flow. On the other hand, the effective gate dielectric thickness could be further reduced by high-k dielectrics, which normally have a k value larger than about 7.0. It seems that the gate-first approaches with the gate stack consisting of high-k dielectrics and metal gates result in the most attractive results. However, the gate-first approaches incur high threshold voltages due to the Fermi level pinning by oxygen vacancies of the high-k dielectric. To solve the Fermi level pinning problem, a capping oxide overlying the high-k dielectric was proposed to produce the dipole field to change work function. Compared to the capping oxide for NMOS devices, there are fewer kinds of capping oxide for PMOS devices and the options have smaller tuning ability. On the other hand, since metal gates are exposed to high temperatures in the annealing of source and drain regions, the work functions of these metallic materials shift, for example, toward the mid-gap level. The gate dielectric work function tuning ability by using metal gates is limited. The performance of the resulting PMOS devices is thus adversely affected.
Various approaches such as adding an oxide cap and performing counter doping have been taken to reduce the threshold voltages for PMOS devices (to reduce the absolute value of the negative threshold voltage). However, the reduction in the threshold voltages is very sensitive to the thickness of the oxide cap. Unfortunately, even if the thickness of the oxide cap can be controlled accurately as formed, the subsequent processes such as the removal of an overlying photo resist (also referred to as a mask, which is used for protecting the oxide cap in PMOS device regions during the removal of the oxide cap from NMOS device regions) may cause loss of or damage to the oxide cap. The threshold voltages and the reliability, e.g., time dependent dielectric breakdown (TDDB), are thus affected.
A further problem in conventional processes is that PMOS devices and NMOS devices often share a same metallic material as metal gates. To comply with the requirement of PMOS devices, the work function of the metallic materials of the metal gates have to meet the requirement of the PMOS devices. However, this results in the performance of the NMOS devices being compromised.
Accordingly, what is needed in the art is a semiconductor structure and respective formation methods that may incorporate metal gates and the gate dielectric thereof to take advantage of the benefits associated with optimized work functions while at the same time overcoming the deficiencies of the prior art.